Chemical mechanical polishing (CMP) of semiconductor wafers has become the preferred method for planarizing dielectric or metallic layers at various stages of integrated circuit fabrication. During the CMP process, a workpiece surface, such as the surface of a semiconductor wafer, is held against a rotating platen. The rotating platen is covered with one or more-slurry-soaked polishing pads. The combination of the chemical interaction of the slurry with the semiconductor wafer and the friction between the polishing pads and the surface of the semiconductor wafer removes material from the wafer. Because of the small dimensions of silicon wafers and the precise surface finishes required and the costs associated with changing polishing pads, there is a need to gain a better understanding of the CMP process by mathematically predicting the results of a chemical mechanical polishing process.
Although the bulk material removal rate of interlevel dielectric materials by a CMP system is heavily chemistry dependent, there is no chemical preference between the high and low areas on the surface of the wafer being polished. Therefore, when using a CMP process on dielectric materials, the planarization of the polished surface of the wafer is due solely to the mechanical action of the polishing pad against the surface of the wafer. And it is this mechanical action which is predictable by the use of pseudo-physical modeling techniques.
CMP systems are often used to process the silicon dioxide dielectric material (commonly referred to as “oxide”) layers from semiconductor wafers. The objective of the use of such CMP systems is to uniformly remove the dielectric material or oxide across the semiconductor wafer being polished such that the small (sub-micron to millimeter) features or surface irregularities that populate the wafer surface are worn away and thereby eliminated. It is important, at the same time, to assure that the overall global characteristics of the wafer surface are maintained. Consequently, the most effective CMP systems provide both wafer scale uniformity (i.e., uniform material removal over the surface of the workpiece) in addition to providing feature scale planarity (i.e., removal of small features or surface irregularities).
In a typical prior art CMP system, as shown in FIG. 1, a polishing pad stack includes a relatively soft base pad and a relatively stiff upper pad (e.g., a polyurethane pad). The upper pad actually contacts the surface of the wafer. The combination of the soft base pad with the relatively stiff upper pad results in a pad stack which is flexible enough to provide uniform material removal or wafer scale uniformity across the surface of a workpiece, yet stiff enough to smooth out the smallest surface irregularities to obtain feature scale planarity. The slurry used for most CMP systems is typically a water based composition which includes suspended colloidal silica particles.
As may be understood by reference to FIGS. 2A and B, CMP is used to planarize the interlevel dielectric material portions of a semiconductor wafer. Typically, the surface of the interlevel dielectric materials on an unpolished semiconductor wafer has a pattern on its surfaces that results from the dielectric material being deposited over a pattern of metal lines. The imbedded metal lines within the dielectric material will form the electrical connections on the surface of the wafer after the dielectric material has been removed by CMP.
As shown in FIGS. 3A and B, a CMP system may alternatively be used to polish away deposited metal films such as tungsten or copper by completely removing them from a dielectric substrate—except for that portion of the deposited layer of tungsten or copper which remains in the trenches which are pre-etched into the underlying dielectric material.
The mechanical aspect of the CMP process in the removal of small surface irregularities or feature scale is the underlying reason why the density of the pattern formed by the imbedded metal lines (FIG. 2) on the surface of the wafer plays a big role in the effectiveness of a CMP process on removing interlevel dielectric materials from the surface of a wafer. In other CMP processes, which are designed to remove surface metal instead of interlevel dielectric materials, the initial planarization of the deposited metal film reflects the topography of the underlying dielectric material. The removal of metal by a CMP system is more dependent on chemistry than on the density of pattern lines. The removal of a deposited metal film by CMP has a chemical preference that results in a natural “polish stop,” wherein the barrier between the resulting main conductor and the dielectric material is relatively resistant to the slurry on the polishing pads. (The slurry is typically custom blended for the type of metal to be removed.) Since polishing is never absolutely perfectly uniform across a wafer surface, the deposited metal remaining in the trenches etched in the dielectric material, from which the conductors are formed, may be “dished out” at the top of the trenches while the last of the barrier layer of deposited metal film is being removed from the surface of the wafer (FIG. 3). Therefore, for this additional reason, the underlying pattern density of the dielectric material plays a significant role in the operation of a CMP process to remove a deposited metal film.
The quality of a finished workpiece subjected to a CMP process may be expressed in terms of both workpiece surface uniformity and workpiece surface planarity. Consequently, the particular CMP process parameters selected, to include: pad rigidity, slurry composition, polish time, relative speed of the wafer and the polishing pad, down force imparted on the wafer carrier, the dynamics of the workpiece carrier motion, etc., assure that the polished workpiece exhibits a desired surface uniformity and surface planarity. For example, the selection of a CMP process parameter such as the use of a comparatively rigid upper pad will tend to planarize the surface of a workpiece better than a comparatively resilient upper pad. Similarly, the selection of a relatively resilient upper pad will provide better global uniformity because it can conform to the overall shape and contour of the workpiece surface.
Many prior art systems developed to mathematically model a CMP process have focused on calculating the CMP system parameters needed to optimize the global uniformity of the finished workpiece without considering the negative effect that such optimization may have on the feature scale planarity of the finished workpiece. The results obtained from such prior art CMP modeling systems fail to effectively strike an optimized balance between both predicting workpiece surface uniformity and workpiece surface planarity.
In the use of CMP processes on interlevel dielectric materials, the term “local planarity”, which is a feature scale measurement, can be used to designate when small surface thickness variations on the surface of the interlevel dielectric material are within a desired tolerance (FIGS. 2A and 2B). The analogous measurement in the use of a CMP process to remove a deposited metal film is the amount of dishing of the deposited metal in the top of the trenches in the dielectric material (FIGS. 3A and 3B). In both types of CMP processes, the need to achieve local planarity requires that material be selectively removed on the feature scale. However, selectivity on the feature scale competes, in turn, with the need for uniform removal of material on the wafer scale. A successful CMP process is one that operates effectively in a CMP process regime to ultimately optimize both the feature scale and the wafer scale measurements on the surface of a polished workpiece.
It is appropriate to mention that other mathematical models directed specifically to feature scale erosion and planarization have been developed. One of the first published feature scale erosion and planarization models appears in the article, “A Two-Dimensional Process Model for Chemical Polish Planarization” by J. Warnock which was published in the August 1991 issue of the Journal of the Electrochemical Society. An extensive review of Dr. Warnock's model reveals that its parameters were heavily dependent on the surface pattern of the wafer, thereby restricting the applicability of Dr. Warnock's model as a predictive tool to a narrow range of applications.
Recently, a closed-form mathematical model describing the relationship between pattern density and the rate of removal of material during the polishing process was published by Stine, et al. in an article entitled “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes” which appeared in the February 1997 CMP-MIC Conference Journal. The Stine, et al. model modifies the pressure distribution used in the Preston equation for material removal rate based on the local pattern density (The Preston equation indicates that the material removal rate during a polishing process is directly proportional to both the force between the wafer and the polishing pad, and the relative speed of the wafer and the polishing pad.).
A feature scale mathematical model based solely on pad compression was recently presented by Grillaert, et al. entitled “Modeling Step Height Reduction and Local Removal Rates Based on Pad-Substrate Interactions” at the February 1998 CMP-MIC Conference. The Grillaert, et al. model represents a superset of the closed-form analytic model disclosed in the Stine, et al. article. While effective for some applications, the Grillaert, et al. model still falls short of achieving accurate prediction of CMP results because it does not account for the flexural bending of the polishing pads. The flexural bending of polishing pads always occurs during an actual polishing process.
The prior art CMP process model disclosed in U.S. Pat. No. 5,599,423, issued to Parker et al., is designed to simulate and ultimately optimize a semiconductor wafer polishing process. The Parker et al. model is based upon experimental techniques to optimize the polishing parameters. In particular, the Parker et al. model iteratively varies the process polishing parameters, measures the actual polishing results associated with each process iteration, and then analyzes the empirical data to suggest an optimized polishing process. However, the Parker et al. model simply optimizes the global uniformity of the wafer surface without regard to the effect that such global optimization of wafer scale uniformity will have on the feature scale planarity of the polished wafer. Due to its inherent limitations, the Parker et al. model is not capable of optimizing the CMP process parameters in accordance with an initial feature scale pattern or in accordance with an intended planarization characteristic of the polished wafer.
Other prior art CMP process modeling or simulation techniques lack the capability to calculate a sufficient number of modeling parameters such that simulation errors can be minimized. Such prior art CMP process modeling or simulation techniques may produce inaccurate simulation results that do not take advantage of the historical empirical data associated with a particular set of CMP process parameters. Furthermore, prior art CMP modeling systems are often limited to use with a particular CMP system configuration. Such CMP modeling systems are limited by not being capable of processing empirical and/or simulated processing results associated with one CMP system configuration to model or design another theoretical CMP system configuration which has a number of different physical characteristics and a number of different process parameters.
Finding and expanding a successful mathematical mode for a CMP process is a critical need for those involved in the engineering of manufacturing processes utilizing CMP. In the past, expensive experimental techniques have been the primary method to define a successful CMP process. Therefore, the ability to reliably model and thereby predict feature scale surface thickness variations or wafer scale material removal without having to rely on expensive actual experimentation techniques is highly desirable. Such a reliable and predictive model could be used to define one or more variables in a CMP process regime. For example, it is well known that a high down-force will generally improve the global uniformity of the wafer scale of the polished surface by providing a more uniform contact between the wafer and the polishing pad, but high down forces on the wafer carrier also decrease the rate of local planarization of feature scale because the polishing pad is forced into more intimate contact with low areas on the surface being polished. Similarly, the use of a comparatively resilient polishing pad stack will produce better uniformity characteristics but poorer planarization capability.
In addition there is a need for a mathematical model for a CMP process which enables the prediction of pad life as proper timing of the need for changing polishing pads minimizes the cost of a CMP process.
Accordingly, a robust, predictive model for a CMP process is needed that can be used to determine, among other CMP process parameters, the optimal wafer carrier down force and the best pad rigidity to produce the desired surface uniformity and planarity on a workpiece for a given CMP process regime.